1. Field of the Invention
The present invention relates generally to power management of computer buses and connected peripheral devices for reduced power consumption. More particularly, the present invention relates to Peripheral Component Interconnect (PCI) bus devices capable of operation before, during and after low power states of an associated PCI bus.
2. Background of Related Art
A computer bus is a set of wires used for data transfer between components of a computer system. Present-day personal computers (PCs), whether in the form of "desktops," "laptops," or "notebooks," use buses optimized for low-cost environments.
A Peripheral Component Interconnect (PCI) bus is a high performance local bus used by many PCs, that provides data paths between the central processing unit (CPU) of the PC and various high speed peripherals. Some peripherals connect to the PCI bus via expansion card slots, and include high-resolution video boards, local area network (LAN) devices, disk controllers, and many others. PCI buses are triple power supply buses (3.3 volts, 5 volts, and -12 volts) which transfer up to 64 bits in parallel at operating speeds of up to 1600 million bytes per second (Mbps), and have either 3.3 volt or 5 volt signaling.
The general specifications and protocols of PCI buses are included in PCI Local Bus Specification, Revision 2.2, dated Dec. 18, 1998, and published by the PCI Special Interest Group, Hillsboro, Oreg., U.S.A., the entirety of which is explicitly incorporated herein by reference.
Moreover, many of the general power management specifications needed for operation of PCI buses are detailed in PCI Special Interest Group's PCI Bus Power Management Interface Specification, Version 1.1, dated Dec. 18, 1998, the entirety of which is also explicitly incorporated herein by reference.
Present PCs may include multiple PCI buses, each being connected to one or more peripheral devices. Generally, a PCI bus remains in its high power state (3.3 or 5 volts) when there is activity or a need for activity by any of its connected peripheral devices. To conserve power, it is desirable to shut off main power to inactive devices on a PCI bus. This is especially true for PCs operating in a battery-powered mode, since battery life is limited. In addition to transferring data and control information between peripheral devices and central processing units (CPUs), or from one peripheral device to another, PCI buses provide clock signals, and provide main power (3.3 or 5 volts). More recently, PCI buses provide auxiliary power (e.g., 3.3 volt Vaux) to connected peripheral devices.
PCI buses operate at a number of defined power savings levels ranging from maximum powered states (D0) to minimum powered states (D3). The D3 state has two sub-states called D3.sub.hot and D3.sub.cold. The difference between D3.sub.cold and D3.sub.hot is that devices in the D3.sub.cold state have had their main power supply turned off.
In a "cold" state, the PCI bus stops supplying main power to the connected peripheral devices to conserve power, although auxiliary power remains available. When a peripheral device connected to a dormant PCI bus needs to operate, it must cause the PCI to "wakeup" and begin re-supplying the main power.
Some conventional devices handle wake-ups from cold states by keeping the entire peripheral device powered by the auxiliary power. While a lower power consumption results, it is not as low as desirable. Further, since most desktop PCs and peripheral devices are designed to operate from 5 volt power sources (rather than from 3.3voltage sources), additional hardware is required, e.g., in the form of a voltage converter. Alternatively, the peripheral device can be specially designed to operate from a 3.3 volt power source, requiring a 5 volt tolerant buffer/interface. Still further, the peripheral device can use a non-PCI bus power supply such as another battery or side-band power supply to power the circuitry in the cold state necessary to activate a signal on the PCI bus (e.g., PME#) to have main power re-applied, increasing the cost, weight and complexity of operation.
FIG. 1 shows an example of a prior art hierarchical bus structure as part of a computer system 100.
The system 100 has a local bus 140 and two PCI buses 160 and 180. It will be appreciated by those skilled in the art that essentially any number of PCI buses can be implemented based on the requirements of the particular application.
The system CPU 102 is connected to the local bus 140 and directly or indirectly performs operations with the other components of the system 100 either via the local bus 142 (such as with the memory 104, which generically represents such common components as DRAMs, cache memory, memory control and the like) or via a bus bridge/controllers 106, 114, connecting to other PCI buses 160, 180.
The PCI buses 160 and 180 are connected in parallel through a bus bridge/controller 114. Additional PCI buses in such a system would also be connected via bus bridge/controllers. Peripherals such as the peripheral device 120 in the system 100 interface with the PCI buses via peripheral controllers (e.g., 108, 110, 116, and 118).
It will be understood by those skilled in the art that many types of connections can be made to the PCI buses, including peripheral devices and memory storage, and even non-PCI buses and local area networks (LANs).
A power management unit (PMU) controller 112 directs PCI power supply control (through clock signals and the like), and implements power conservation algorithms to conserve power when full power is not needed by peripheral devices and PCI buses. PCI bus specifications require a 3.3 volt and/or 5 volt main power supply and define an optional 3.3 volt auxiliary power supply.
In the so-called D3.sub.cold state of a PCI bus, main power to the connected peripherals is shut down for maximum bus power efficiency to conserve power consumption. The D3.sub.cold state is only indicated where no operation of connected peripheral devices is contemporaneously needed.
There is a need for apparatus and a technique for allowing maximum efficiency in power usage during a low power state such as the D3cold state defined for the PCI bus, while still allowing the low-powered peripheral device to itself request that main power be re-applied.